ModelSim SE software for simulation and debug environment, combining
high performance with the most powerful and intuitive GUI in the
industry.
Full details Modelsim SE 10.1c and get links download please reading below.
Mentor
Graphics was the first to combine single kernel simulator (SKS)
technology with a unified debug environment for Verilog, VHDL, and
SystemC. The combination of industry-leading, native SKS performance
with the best integrated debug and analysis environment make ModelSim
the simulator of choice for both ASIC and FPGA design. The best
standards and platform support in the industry make it easy to adopt in
the majority of process and tool flows.
High Performance and Capacity Mixed HDL Simulation
ModelSim combines
high performance and high capacity with the code coverage and debugging
capabilities required to simulate larger blocks and systems and attain
ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and
SystemC provide a solid foundation for single and multi-language design
verification environments.
The ModelSim vopt usage mode achieves
industry-leading performance and capacity through very aggressive,
global compile and simulation optimization algorithms of Verilog and
VHDL, improving Verilog and mixed VHDL/Verilog RTL simulation
performance by up to 10X. The performance mode can also improve Verilog
gate-level performance by up to 4X and capacity by over 2X. ModelSim
also supports very fast time-to-next simulation and effective library
management while maintaining high performance with its new black box use
model, known as bbox. With bbox, non-changing elements can be compiled
and optimized once and reused when running a modified version of the
testbench. bbox delivers dramatic throughput improvements of up to 3X
when running a large suite of testcases
Effective Debug Environment
ModelSim
eases the process of finding design defects with an intelligently
engineered debug environment. The ModelSim debug environment efficiently
displays design data for analysis and debug of all languages.
ModelSim
allows many debug and analysis capabilities to be employed
post-simulation on saved results, as well as during live simulation
runs. For example, the coverage viewer analyzes and annotates source
code with code coverage results, including FSM state and transition,
statement, expression, branch, and toggle coverage. Signal values can be
annotated in the source window and viewed in the waveform viewer,
easing debug navigation with hyperlinked navigation between objects and
its declaration and between visited files. Race conditions, delta, and
event activity can be analyzed in the list and wave windows.
User-defined enumeration values can be easily defined for quicker
understanding of simulation results. For improved debug productivity,
ModelSim also has graphical and textual dataflow capabilities.
The
ModelSim debug environments broad set of intuitive capabilities for
Verilog, VHDL, and SystemC make it the choice for ASIC and FPGA design.
Advanced Code Coverage
The
ModelSim advanced code coverage capabilities provide valuable metrics
for systematic verification. All coverage information is stored in the
Unified Coverage DataBase (UCDB), which is used to collect and manage
all coverage information in a highly efficient database. Coverage
utilities that analyze code coverage data, such as merging and test
ranking, are available. Coverage results can be viewed interactively,
post-simulation, or after a merge of multiple simulation runs. Code
coverage metrics can be reported by instance or by design unit,
providing flexibility in managing coverage data.
